Periods/week : 3 Periods & 1 Tut /week.                                                                  Ses. : 30 Exam : 70 Examination (Practical): 3hrs.                                                                                   Credits: 4

1.    Overview of Digital Design with Vermilion HDL

2.    Hierarchical Modeling Concepts

3.    Basic Concepts

4.    Modules and ports

5.    Gate-Level Modeling

6.    Dataflow Modeling

7.    Behaviour Modeling

8.    Tasks and Functions

tejus mahiCSE 3.2 SyllabusCSE,CSE Syllabus,IT,IT Syllabus,VHDL Syllabus
Periods/week : 3 Periods & 1 Tut /week.                                                                  Ses. : 30 Exam : 70 Examination (Practical): 3hrs.                                                                                   Credits: 4 1.    Overview of Digital Design with Vermilion HDL 2.    Hierarchical Modeling Concepts 3.    Basic Concepts 4.    Modules and ports 5.   ...